For placement and routing of integrated circuits, as well as other design functions, it is necessary to meet timing parameters based on certain assumptions about circuit delay. However, conventionally, delay of a signal through transistor gates in an integrated circuit varies with voltage, temperature and process. Thus, assumptions about timing may need to be varied based on actual performance of an integrated circuit within an operating environment.
Clock phase or clock period is conventionally used to measure composite delay through similar logic elements. A total delay for a whole clock phase is then divided into the number of logic elements used to achieve such a whole clock phase delay. This division results in a delay value ascribed to each individual delay element, such as for a delay line in a delay locked loop (“DLL”). This solution is satisfactory for a significant number of same circuit elements chained together in series and matched with respect to process, voltage and temperature. However, this is not meaningful with respect to disparate circuit elements, which may not be chained together in series and which may have voltage, temperature and process variation differences.
Accordingly, it would be desirable and useful to be able to characterize delay of circuit elements of an integrated circuit within an operating environment.